مميزات خاصة

Medium-speed operation, Fully static operation
Buffered inputs and outputs, 100% tested for quiescent current at 20 V, Standardized, symmetrical output characteristics
Common reset, 5-V, 10-V, and 15-V parametric ratings, Maximum input current of 1 µA at 18 V over full package-temperature range; 100 nA at 18 V and 25°C
Noise margin (over full package-temperature range): 1 V at VDD = 5 V, 2 V at VDD = 10 V, 2.5 V at VDD = 15 V
Meets all requirements of JEDEC Tentative Standard No. 13B, "Standard Specifications for Description of 'B' Series CMOS Devices", Applications: Control counters Timers Frequency dividers Time-delay circuits

وصف

The CD4040B are ripple-carry binary counters. All counter stages are master-slave flip-flops. The state of a counter advances one count on the negative transition of each input pulse; a high level on the RESET line resets the counter to its all zeros state. Schmitt trigger action on the input-pulse line permits unlimited rise and fall times. All inputs and outputs are buffered.

منتجات شبيهه

{"error":"\u062e\u0637\u0623","cart_limit":"\u0644\u062f\u064a\u0643 \u0627\u0644\u0643\u062b\u064a\u0631 \u0645\u0646 \u0627\u0644\u0645\u0646\u062a\u062c\u0627\u062a \u0641\u064a \u0633\u0644\u0629 \u0627\u0644\u062a\u0633\u0648\u0642 \u0627\u0644\u062e\u0627\u0635\u0629 \u0628\u0643.","prod_limit":"\u0644\u0627 \u064a\u0645\u0643\u0646\u0643 \u0625\u0636\u0627\u0641\u0629 \u0627\u0644\u0645\u0632\u064a\u062f \u0645\u0646 \u0647\u0630\u0627 \u0627\u0644\u0645\u0646\u062a\u062c"}

مرحبًا،

بحث

CD4040BE CD4040 CMOS 12 مرحلة تموج العداد الثنائي/مقسمات الصديقة للوحة IC DIP-16 (حزمة 5)

مميزات خاصة

وصف

منتجات شبيهه