Introduction

-The main chip of RV-debugger-plus is BL702 32-bit RISC-V CPU, integrated BLE, reserved antenna pads, which are not supported by firmware
-RV-debugger-plus integrates JTAG debugging interface, which can debug bare metal, UBOOT, LINUX kernel, etc. through JTAG protocol
-JTAG adopts the FDTI protocol, which requires no driver installation but requires Win10 or Linux kernel version 4.X or above
-Rv-debugger-plus integrates USB to TTL debugging serial port, supports 5V/3.3V dual output, and the default level of TTL and JTAG is 3.3V.
-RV-debugger-plus uses 5V@500mA/3.3V@200mA for external power supply, of which 5V is directly connected to USB through 0.6A fuse, and 3.3V is provided by onboard LDO.
-RV-debugger-plus adopts USB Type-C interface, users need to prepare their own USB Type-c data cable
-RV-debugger-plus uses 2.54mm pitch pin headers, in order to facilitate the use of DuPont lines to connect the target board for debugging.
-RV-debugger-plus has a relatively small size, with a size of 42*16*9.3mm.
-RV-debugger-plus supports the secondary development of Bouffalo Lab SDK, but Sipeed does not provide technical support.

Hardware Description
The RV debugger has a total of 14 pins, and the 10 pins at the tail have been soldered to the factory
3V3: 3.3V power supply output GND: System power ground TX: Virtual serial port (UART1) transmitter, the default level is 3.3V RX: virtual serial port (UART) receiving end, the default level is 3.3V DTR: virtual serial port (UART1) data terminal ready terminal, the default level is 3.3V RTS: virtual serial port (UART1) request sender, the default level is 3.3V 5v: 5.OV power output GND: System power ground TCK: JAG test clock input, the default level is 3.3V TDI: JTGA test data input, the default level is 3.3V TDo: JTGA test data output, the default level is 3.3V TMS: JTGA test mode selection, the default level is 3